PXI backplanes

Image for PXI backplanes from Schroff - Asia Pacific
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  • 12-layer structure, min. crosstalk digital to analogue section
  • 64-bit CompactPCI bus and PXI bus on the P2 plane
  • In accordance with: PXI Specification R 2.0, PICMG 2.0 R3.0 CompactPCI Core Specification, PICMG 2.1 R2.0 Hot-swap Specification, PICMG 2.9 R1.0 System Management Bus Specification, PICMG 2.10 R1.0 Keying Specification
  • Utility connector for status signals
  • Intelligent platform management bus (IPMB) connector to PICMG 2.9
  • Clock generated on the backplane; feeding in an external clock is possible, the backplane switches automatically between the two clocks
  • Outstanding high-frequency noise suppression and very high MTBF values due to ceramic capacitors
  • Backplanes with up to 5 slots are capable of 66 MHz, 6 to 8 slot backplanes are set to 33 MHz operation

    Specification:

    PXI

Select product specifications before modifying or adding to project list or requesting a quote.

Width mm
Number of Slots
 
Catalog Number Number of slots System slot Width mm System slot Rear I/O Description Height U No. of layers
Catalog Number Number of slots System slot Width mm System slot Rear I/O Description Height U No. of layers
5 left 100.6 right no 64-bit CompactPCI bus, PXI bus 3 12
7 left 141.0 right no 64-bit CompactPCI bus, PXI bus 3 12
8 left 162.0 right no 64-bit CompactPCI bus, PXI bus 3 12